The services required are Physical design engineers who are experts in the full digital IC design flow and specifically in floor planning, the complete Place and Route flow, Signoff Static Timing Analysis, Timing closure activities and physical verification.
The scope of work includes the physical implementation of blocks in advanced TSMC processes (7nm and below), specifically, the following aspects of the physical flow:
• Topographical synthesis of physical partitions
• Create clock constraints & perform block level clock tree synthesis
• Ownership of block level timing closure activities
• Floor-planning of the blocks
• Complete place & route of the blocks
• Physical verification of the blocks
• Signoff STA of the blocks
• Responsible for identifying any RTL/documentation/flow bugs and logging bug reports for tracking purposes
• Responsible for closing bug reports in a timely manner
• Responsible for ensuring that there are no bugs found that would necessitate a stepping in the project.
• Responsible for identifying design bugs and closing them off comprehensively or by clearly handing over to an acceptable owner
• Work closely with & support RTL, DFX and physical teams
• PT & ICC2 environment maintenance and updates as necessary.